1. Field of the Invention
The present invention relates in general to an electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to an ESD protection circuit suitable for application in an integrated circuit (IC).
2. Description of the Related Art
FIG. 1 shows a conventional ESD protection circuit of an IC. The ESD protection circuit 10 has an NMOS NESD coupled between a pad 12 and a power line VSS. A RC coupling circuit is formed by a capacitor C and a resistor R in the circuit. When an ESD voltage, positive with respect to the power line VSS occurs at the pad 12, a positive voltage is coupled to a gate of the NMOS NESD enhancing the triggering rate of the NMOS NESD. Generally, an IC chip with ESD protection circuits must sustains more than the minimum human-body-mode (HBM) ESD stress, 2 k volts. However, when the gate of the NMOS NESD is over- or under-stressed, ESD protection of ICs provided by the ESD protection circuit in FIG. 1 is compromised. FIG. 2 shows a fixed voltage applied to the gate of the NMOS NESD in FIG. 1. An experimental result of voltages at the gate of the NMOS NESD against the highest voltage NESD can sustain is shown in FIG. 3. Voltages applied to the gate of the NMOS NESD allow a triggering voltage of the NMOS NESD to decreaseer. As shown in FIG. 3, when bias voltages at the gate of the NOS NESD is small and is increased, ESD stress sustainable by the NMOS NESD increases. Nevertheless, when bias voltages at the gate of the NMOS NESD passes an optimized point and is overly increased, large ESD current crossing a thin channel under the NMOS NESD easily damages the NOS NESD and causes ESD level sustained by the NMOS NESD to drop. ESD protection provided by the circuit in FIG. 2 is optimized by bringing a bias voltage at the gate of the NMOS NESD to a specified amplitude, such as VGopt in FIG. 3. Therefore, it has become an object for circuit designers to bring bias voltages at the gate of the NMOS NESD in FIG. 1 to the specified amplitude VGopt during an ESD event.
The ESD protection circuit in FIG. 1 may be unreliable during an ESD event. Capacitances of parasitic capacitors, such as Cgd and Cgs, formed in the NMOS NESD sway during different manufacturing processes. Voltages coupled from ESD stress at the pad 12 to the gate of the NMOS NESD are undoubtedly affected by the changing capacitances. In addition, ESD stresses occur on the pad 12 at different rates. Therefore, voltages coupled to the gate of the NMOS NESD are unpredictable, resulting in unreliable performance. For instance, the circuit in FIG. 1 might have sustained a HBM ESD stress of 5 kv, but fails to sustain a HBM ESD stress of 2 kv. Voltages at the gate of the NMOS NESD in the circuit of FIG. 1 are thus hard to control and are unpredictable during a manufacturing process.